CA-San Francisco, Job Title: ASIC Design Engineer/ RTL Design Engineer Duration: Full Time Location: Bay Area, CA Job description : Logic design /micro-architecture / RTL coding is a must. Expertise in Verilog & System Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus. Hands

Tagged as: design, IT

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